As very large scale integrated (VLSI) circuits move toward a lower 3.3 volt power supply voltage, conventional analog complementary metal oxide semiconductor (CMOS) circuits lose a significant amount of operating range. One of the more commonly used analog circuits which is most strongly affected by the reduced power supply is an input stage differential pair of an operational amplifier (opamp). The input stage differential pair of an opamp may have a common mode input range of only half of the full power supply range.
A rail-to-rail CMOS differential input stage, as shown in FIG. 1, is commonly used to take advantage of the entire 3.3 volt input range and provides at least one output signal which is a function of the first and second input voltage signals. This conventional input stage includes a first pair of field effect transistors (FETs) M.sub.n1, M.sub.n2 of one conductivity type, connected in parallel with a second pair of FETs M.sub.p1, M.sub.p2 of an opposite conductivity type. The subscript "n" denotes n-type conductivity, and the subscript "p" denotes p-type conductivity. A first differential input, V.sub.in1, is connected to the gates of FETs M.sub.p1 and M.sub.n1, and a second differential input, V.sub.in2, is connected to the gates of FETs M.sub.p2 and M.sub.n2. The drains of the p-type FETs furnish two current outputs I.sub.out1 and I.sub.out2, and the drains of the n-type FETs supply two more current outputs I.sub.out3 and I.sub.out4. A constant bias current, I.sub.p, flows from the reference voltage source V.sub.dd into the sources of the p-type FETs M.sub.p1 and M.sub.p2. Another constant bias current, I.sub.n, flows from the sources of the n-type FETs M.sub.n1 and M.sub.n2. The output current of the circuit is: EQU I.sub.out =I.sub.outp -I.sub.outn =-V.sub.in (g.sub.mn +g.sub.mp)=-V.sub.in g.sub.mT
where g.sub.mT, the total transconductance, is: EQU g.sub.mT =g.sub.mn +g.sub.mp
where g.sub.mn is the transconductance of the n-type FETs, and g.sub.mp is the transconductance of the p-type FETs.
The output currents of the differential pairs, I.sub.outp and I.sub.outn, are defined by: EQU I.sub.outp =I.sub.out1 -I.sub.out2 =-g.sub.mp V.sub.in I.sub.outn =I.sub.out3 -I.sub.out4 =g.sub.mn V.sub.in
Unfortunately, however, for fixed bias currents I.sub.p and I.sub.n, the transconductance, g.sub.m, of the input stage varies by at least a factor of two over the common mode range. The frequency compensation is therefore more complicated, and the frequency response is limited, because the unity gain frequency of the opamp is proportional to the transconductance of the input stage. A constant transconductance, on the other hand, ensures a steady unity gain frequency within the whole common mode input range.
For an n-type MOS transistor operating in the saturation region, the drain current equation is: EQU I.sub.d =K(V.sub.gs -V.sub.T).sup.2 ( 1)
where, V.sub.gs, is the transistor's gate to source voltage;
V.sub.T, is the transistor's threshold voltage; and
K, the device transconductance parameter, =.mu.C.sub.ox W/2L;
where, C.sub.ox, is the capacitance of the gate oxide; PA2 W, is the channel width; and PA2 L, is the channel length.
Significantly, the mobility .mu. of an electron is 2 to 3 times larger than that of a hole. Thus, if one wishes to obtain similar current to voltage characteristics from both an n-type MOSFET and a p-type MOSFET, the size of the p-channel transistor must be 2 to 3 times that of the n-channel transistor. The transconductance of a transistor with K.sub.i and I.sub.d is: ##EQU1## The total transconductance, g.sub.mT, of the circuit in FIG. 1 is thus: ##EQU2## Where K.sub.n I.sub.n is the device transconductance parameter and current, respectively, in the n-channel transistors and K.sub.p I.sub.p is the device transconductance parameter and current, respectively, in the p-channel transistors. Both terms on the right side of equation (3) are constant for only a small region of the common mode range because the current sources will be pushed into the triode region as the input voltage moves toward the supply rails.
The conventional approach using equation (1) in designing a constant g.sub.m input stage, as in FIG. 1, was to assume that n-channel and p-channel transistors can be matched (K.sub.n =K.sub.p can actually be achieved). If so, then equation (3) can be rewritten as: ##EQU3## In the past, a dynamic bias circuit which maintains the sum of the square-roots of I.sub.n and I.sub.p was used to keep the circuit's g.sub.mT constant. For a review of this type of design, see, R. Hogervorst, R. J. Wiegerinkk, P. A. de Jong, J. Fonderie, R. F. Wassenaar, and J. H. Huijsing, "CMOS low-voltage operational amplifiers with constant-g.sub.m rail-to-rail input stage," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2876-2879 (1992). The major disadvantage of this variety of circuits is that the matching of transistors of opposite conductivity types is assumed. In reality, the K.sub.n /K.sub.p ratio can vary by more than 20% between transistor fabrication runs within the same batch process.